1. Field of the Invention
This invention relates to digital read/write memory, and more particularly to a hybrid of content addressable and random access memory.
2. Description of the Related Art
The most common type of digital read/write memory is random access memory (RAM). RAM is responsive to an address bus and a control bus, and generally has a bidirectional data bus. An. address is put on the address bus by a central processing unit (CPU), direct memory access (DMA) device, or other addressing device to specify a unique storage location within the RAM. The addressing mechanism of a RAM is said to be unambiguous since each address on the address bus specifies one and only one storage location within the RAM.
While RAM is well suited for many digital applications, it is not particularly well suited for use in systems which process associative data. For example, the sequential access to data when addressing RAM can be inefficient for systems involved in pattern recognition, natural language recognition, sparse matrix processing, and database interrogation.
A type of digital read/write memory which is better suited for systems which process associative data is known as content addressable memory (CAM). Storage locations within CAM are addressed simultaneously and in parallel by an incoming bit pattern called a comparand. Part of the contents of each storage location within the CAM can be considered to be an address field, where the remainder of the storage location can be considered to be an associated data field. When the associated data field is used to address another device, it is sometimes called a pointer field and is said to contain a pointer address.
With a CAM the comparand is compared, in parallel, to the address fields of all storage locations, and if the address fields have the desired relationship to the comparand the associated data field at that location can be accessed. Alternatively, the comparand can be compared to the entirety of each of the storage locations to detect whether the the particular bit pattern corresponding to the comparand is stored within the CAM, in which case the presence or absence of the comparand amongst the contents is indicated by a Boolean output signal (flag).
A typical CAM includes a comparand input bus, a control input bus, a valid match output, and a bidirectional data bus. A number of comparison operations built into the CAM and selected by the control bus may be allowable, including equality, inequality, less than, greater than, etc.
CAM, as opposed to RAM, may have ambiguous addresses. In other words, a number of address fields within the CAM may hold the same contents. If ambiguous addressing is allowed, then multiple responses will result upon a compare. Multiple responses from a CAM are usually accessed serially.
The amount of memory required by a digital system is often greater than that available on a single device. Furthermore, by being able to build a memory system from a number of memory devices the architecture of the memory system is not limited by the architecture of the memory device. In consequence, a number of individual memory devices are commonly connected horizontally and/or vertically in a matrix configuration. The horizontal connection of memory elements increases the effective width of a stored word of memory, and the vertical connection of memory elements increases the number of memory locations available in the memory system.
With RAM memory, the methods for horizontally and vertically connecting memory devices are well known. The vertical connection of CAM elements is likewise a straightforward matter. However, engineers attempting the horizontal cascading of CAM elements have had trouble in achieving their goals because of the difficulties involved in conveying match information between the CAM elements. In the past, the conveyance of match information required multi-cycle comparisons of the individual devices, or an unacceptably large number of intersubfield bus lines.
The only known commercially available CAM device which provides a solution to the horizontal cascading problem is the Fairchild F100142 4.times.4 CAM, which has one open emitter line associated with each memory location to convey intersubfield linking information. This solution requires one pin per memory location for intersubfield communication, resulting in a chip of very low data storage capacity. For example, using the Fairchild F100142 device, a modest 1 K.times.16 CAM system would require 1024 devices, each residing in a 28 pin package and consuming up to 288 mA at 4.2 V. This hypothetical memory system would therefore consume over 1.2 kilowatts of power. Such a system is inappropriate for most applications.
CAM devices are relatively more expensive than RAM devices of the same storage capacity. One reason for this is that the circuitry of CAM is intrinsically more complex than the circuitry of RAM. Each memory cell within a CAM must have both storage capabilities and comparison capabilities, while RAM only needs to have the storage capabilities. Furthermore, the control logic of a CAM tends to be more complex than the control logic of a RAM. Another reason for the cost disparity between the two types of devices is that many more RAM devices are manufactured than CAM devices, allowing for lower production costs for RAM.